VER_NO: f7765f0ac3faf4b54f8c1f064307522c
EFUSES:
  WR_DIS                           : {show: y, blk : 0, word: 0, pos : 0, len : 32, start  : 0, type : 'uint:32', wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: Disable programming of individual eFuses, rloc: EFUSE_RD_WR_DIS_REG, bloc: 'B0,B1,B2,B3'}
  RD_DIS                           : {show: y, blk : 0, word: 1, pos : 0, len  : 7, start : 32, type  : 'uint:7', wr_dis   : 0, rd_dis: null, alt                            : '', dict             : '', desc: Disable reading from BlOCK4-10, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[6:0]', bloc: 'B4[6:0]'}
  USB_DEVICE_EXCHG_PINS            : {show: y, blk : 0, word: 1, pos : 7, len  : 1, start : 39, type      : bool, wr_dis  : 30, rd_dis: null, alt                            : '', dict             : '', desc: Enable usb device exchange pins of D+ and D-, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[7]', bloc: 'B4[7]'}
  USB_OTG11_EXCHG_PINS             : {show: y, blk : 0, word: 1, pos : 8, len  : 1, start : 40, type      : bool, wr_dis  : 30, rd_dis: null, alt                            : '', dict             : '', desc: Enable usb otg11 exchange pins of D+ and D-, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[8]', bloc: 'B5[0]'}
  DIS_USB_JTAG                     : {show: y, blk : 0, word: 1, pos : 9, len  : 1, start : 41, type      : bool, wr_dis   : 2, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[9]', bloc: 'B5[1]'}
  POWERGLITCH_EN                   : {show: y, blk : 0, word: 1, pos: 10, len  : 1, start : 42, type      : bool, wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether power glitch function is enabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[10]', bloc: 'B5[2]'}
  DIS_USB_SERIAL_JTAG              : {show: n, blk : 0, word: 1, pos: 11, len  : 1, start : 43, type      : bool, wr_dis   : 2, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[11]', bloc: 'B5[3]'}
  DIS_FORCE_DOWNLOAD               : {show: y, blk : 0, word: 1, pos: 12, len  : 1, start : 44, type      : bool, wr_dis   : 2, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[12]', bloc: 'B5[4]'}
  SPI_DOWNLOAD_MSPI_DIS            : {show: y, blk : 0, word: 1, pos: 13, len  : 1, start : 45, type      : bool, wr_dis   : 2, rd_dis: null, alt                            : '', dict             : '', desc: Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during boot_mode_download, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[13]', bloc: 'B5[5]'}
  DIS_TWAI                         : {show: y, blk : 0, word: 1, pos: 14, len  : 1, start : 46, type      : bool, wr_dis   : 2, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[14]', bloc: 'B5[6]'}
  JTAG_SEL_ENABLE                  : {show: y, blk : 0, word: 1, pos: 15, len  : 1, start : 47, type      : bool, wr_dis   : 2, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio34 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[15]', bloc: 'B5[7]'}
  SOFT_DIS_JTAG                    : {show: y, blk : 0, word: 1, pos: 16, len  : 3, start : 48, type  : 'uint:3', wr_dis  : 31, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[18:16]', bloc: 'B6[2:0]'}
  DIS_PAD_JTAG                     : {show: y, blk : 0, word: 1, pos: 19, len  : 1, start : 51, type      : bool, wr_dis   : 2, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[19]', bloc: 'B6[3]'}
  DIS_DOWNLOAD_MANUAL_ENCRYPT      : {show: y, blk : 0, word: 1, pos: 20, len  : 1, start : 52, type      : bool, wr_dis   : 2, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[20]', bloc: 'B6[4]'}
  USB_DEVICE_DREFH                 : {show: n, blk : 0, word: 1, pos: 21, len  : 2, start : 53, type  : 'uint:2', wr_dis  : 30, rd_dis: null, alt                            : '', dict             : '', desc: USB intphy of usb device signle-end input high threshold; 1.76V to 2V. Step by 80mV, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[22:21]', bloc: 'B6[6:5]'}
  USB_OTG11_DREFH                  : {show: n, blk : 0, word: 1, pos: 23, len  : 2, start : 55, type  : 'uint:2', wr_dis  : 30, rd_dis: null, alt                            : '', dict             : '', desc: USB intphy of usb otg11 signle-end input high threshold; 1.76V to 2V. Step by 80mV, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[24:23]', bloc: 'B6[7],B7[0]'}
  USB_PHY_SEL                      : {show: y, blk : 0, word: 1, pos: 25, len  : 1, start : 57, type      : bool, wr_dis  : 30, rd_dis: null, alt                            : '', dict             : '', desc: TBD, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[25]', bloc: 'B7[1]'}
  KM_HUK_GEN_STATE                 : {show: y, blk : 0, word: 1, pos: 26, len  : 9, start : 58, type  : 'uint:9', wr_dis  : 19, rd_dis: null, alt                            : '', dict             : '', desc: Set this bit to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[31:26]', bloc: 'B7[7:2],B8[2:0]'}
  KM_RND_SWITCH_CYCLE              : {show: y, blk : 0, word: 2, pos : 3, len  : 2, start : 67, type  : 'uint:2', wr_dis   : 1, rd_dis: null, alt                            : '', dict             : '', desc: 'Set bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles', rloc: 'EFUSE_RD_REPEAT_DATA1_REG[4:3]', bloc: 'B8[4:3]'}
  KM_DEPLOY_ONLY_ONCE              : {show: y, blk : 0, word: 2, pos : 5, len  : 4, start : 69, type  : 'uint:4', wr_dis   : 1, rd_dis: null, alt                            : '', dict             : '', desc: 'Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds', rloc: 'EFUSE_RD_REPEAT_DATA1_REG[8:5]', bloc: 'B8[7:5],B9[0]'}
  FORCE_USE_KEY_MANAGER_KEY        : {show: y, blk : 0, word: 2, pos : 9, len  : 4, start : 73, type  : 'uint:4', wr_dis   : 1, rd_dis: null, alt                            : '', dict             : '', desc: 'Set each bit to control whether corresponding key must come from key manager.. 1 is true; 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds', rloc: 'EFUSE_RD_REPEAT_DATA1_REG[12:9]', bloc: 'B9[4:1]'}
  FORCE_DISABLE_SW_INIT_KEY        : {show: y, blk : 0, word: 2, pos: 13, len  : 1, start : 77, type      : bool, wr_dis   : 1, rd_dis: null, alt                            : '', dict             : '', desc: Set this bit to disable software written init key; and force use efuse_init_key, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[13]', bloc: 'B9[5]'}
  XTS_KEY_LENGTH_256               : {show: y, blk : 0, word: 2, pos: 14, len  : 1, start : 78, type      : bool, wr_dis   : 1, rd_dis: null, alt                            : '', dict             : '', desc: Set this bit to configure flash encryption use xts-128 key; else use xts-256 key, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[14]', bloc: 'B9[6]'}
  RESERVE_0_79                     : {show: n, blk : 0, word: 2, pos: 15, len  : 1, start : 79, type      : bool, wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[15]', bloc: 'B9[7]'}
  WDT_DELAY_SEL                    : {show: y, blk : 0, word: 2, pos: 16, len  : 2, start : 80, type  : 'uint:2', wr_dis   : 2, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected', rloc: 'EFUSE_RD_REPEAT_DATA1_REG[17:16]', bloc: 'B10[1:0]'}
  SPI_BOOT_CRYPT_CNT               : {show: y, blk : 0, word: 2, pos: 18, len  : 3, start : 82, type  : 'uint:3', wr_dis   : 4, rd_dis: null, alt                            : '', dict: '{0: "Disable", 1: "Enable", 3: "Disable", 7: "Enable"}', desc: Enables flash encryption when 1 or 3 bits are set and disables otherwise, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[20:18]', bloc: 'B10[4:2]'}
  SECURE_BOOT_KEY_REVOKE0          : {show: y, blk : 0, word: 2, pos: 21, len  : 1, start : 85, type      : bool, wr_dis   : 5, rd_dis: null, alt                            : '', dict             : '', desc: Revoke 1st secure boot key, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[21]', bloc: 'B10[5]'}
  SECURE_BOOT_KEY_REVOKE1          : {show: y, blk : 0, word: 2, pos: 22, len  : 1, start : 86, type      : bool, wr_dis   : 6, rd_dis: null, alt                            : '', dict             : '', desc: Revoke 2nd secure boot key, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[22]', bloc: 'B10[6]'}
  SECURE_BOOT_KEY_REVOKE2          : {show: y, blk : 0, word: 2, pos: 23, len  : 1, start : 87, type      : bool, wr_dis   : 7, rd_dis: null, alt                            : '', dict             : '', desc: Revoke 3rd secure boot key, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[23]', bloc: 'B10[7]'}
  KEY_PURPOSE_0                    : {show: y, blk : 0, word: 2, pos: 24, len  : 4, start : 88, type  : 'uint:4', wr_dis   : 8, rd_dis: null, alt                  : KEY0_PURPOSE, dict             : '', desc: Represents the purpose of Key0, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[27:24]', bloc: 'B11[3:0]'}
  KEY_PURPOSE_1                    : {show: y, blk : 0, word: 2, pos: 28, len  : 4, start : 92, type  : 'uint:4', wr_dis   : 9, rd_dis: null, alt                  : KEY1_PURPOSE, dict             : '', desc: Represents the purpose of Key1, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[31:28]', bloc: 'B11[7:4]'}
  KEY_PURPOSE_2                    : {show: y, blk : 0, word: 3, pos : 0, len  : 4, start : 96, type  : 'uint:4', wr_dis  : 10, rd_dis: null, alt                  : KEY2_PURPOSE, dict             : '', desc: Represents the purpose of Key2, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[3:0]', bloc: 'B12[3:0]'}
  KEY_PURPOSE_3                    : {show: y, blk : 0, word: 3, pos : 4, len  : 4, start: 100, type  : 'uint:4', wr_dis  : 11, rd_dis: null, alt                  : KEY3_PURPOSE, dict             : '', desc: Represents the purpose of Key3, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[7:4]', bloc: 'B12[7:4]'}
  KEY_PURPOSE_4                    : {show: y, blk : 0, word: 3, pos : 8, len  : 4, start: 104, type  : 'uint:4', wr_dis  : 12, rd_dis: null, alt                  : KEY4_PURPOSE, dict             : '', desc: Represents the purpose of Key4, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[11:8]', bloc: 'B13[3:0]'}
  KEY_PURPOSE_5                    : {show: y, blk : 0, word: 3, pos: 12, len  : 4, start: 108, type  : 'uint:4', wr_dis  : 13, rd_dis: null, alt                  : KEY5_PURPOSE, dict             : '', desc: Represents the purpose of Key5, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[15:12]', bloc: 'B13[7:4]'}
  SEC_DPA_LEVEL                    : {show: y, blk : 0, word: 3, pos: 16, len  : 2, start: 112, type  : 'uint:2', wr_dis  : 14, rd_dis: null, alt                            : '', dict             : '', desc: Represents the spa secure level by configuring the clock random divide mode, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[17:16]', bloc: 'B14[1:0]'}
  ECDSA_ENABLE_SOFT_K              : {show: y, blk : 0, word: 3, pos: 18, len  : 1, start: 114, type      : bool, wr_dis  : 17, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[18]', bloc: 'B14[2]'}
  CRYPT_DPA_ENABLE                 : {show: y, blk : 0, word: 3, pos: 19, len  : 1, start: 115, type      : bool, wr_dis  : 14, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[19]', bloc: 'B14[3]'}
  SECURE_BOOT_EN                   : {show: y, blk : 0, word: 3, pos: 20, len  : 1, start: 116, type      : bool, wr_dis  : 15, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[20]', bloc: 'B14[4]'}
  SECURE_BOOT_AGGRESSIVE_REVOKE    : {show: y, blk : 0, word: 3, pos: 21, len  : 1, start: 117, type      : bool, wr_dis  : 16, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[21]', bloc: 'B14[5]'}
  RESERVE_0_118                    : {show: n, blk : 0, word: 3, pos: 22, len  : 1, start: 118, type      : bool, wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[22]', bloc: 'B14[6]'}
  FLASH_TYPE                       : {show: y, blk : 0, word: 3, pos: 23, len  : 1, start: 119, type      : bool, wr_dis  : 18, rd_dis: null, alt                            : '', dict             : '', desc: 'The type of interfaced flash. 0: four data lines; 1: eight data lines', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[23]', bloc: 'B14[7]'}
  FLASH_PAGE_SIZE                  : {show: y, blk : 0, word: 3, pos: 24, len  : 2, start: 120, type  : 'uint:2', wr_dis  : 18, rd_dis: null, alt                            : '', dict             : '', desc: Set flash page size, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[25:24]', bloc: 'B15[1:0]'}
  FLASH_ECC_EN                     : {show: y, blk : 0, word: 3, pos: 26, len  : 1, start: 122, type      : bool, wr_dis  : 18, rd_dis: null, alt                            : '', dict             : '', desc: Set this bit to enable ecc for flash boot, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[26]', bloc: 'B15[2]'}
  DIS_USB_OTG_DOWNLOAD_MODE        : {show: y, blk : 0, word: 3, pos: 27, len  : 1, start: 123, type      : bool, wr_dis  : 18, rd_dis: null, alt                            : '', dict             : '', desc: Set this bit to disable download via USB-OTG, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[27]', bloc: 'B15[3]'}
  FLASH_TPUW                       : {show: y, blk : 0, word: 3, pos: 28, len  : 4, start: 124, type  : 'uint:4', wr_dis  : 18, rd_dis: null, alt                            : '', dict             : '', desc: Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[31:28]', bloc: 'B15[7:4]'}
  DIS_DOWNLOAD_MODE                : {show: y, blk : 0, word: 4, pos : 0, len  : 1, start: 128, type      : bool, wr_dis  : 18, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[0]', bloc: 'B16[0]'}
  DIS_DIRECT_BOOT                  : {show: y, blk : 0, word: 4, pos : 1, len  : 1, start: 129, type      : bool, wr_dis  : 18, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[1]', bloc: 'B16[1]'}
  DIS_USB_SERIAL_JTAG_ROM_PRINT    : {show: y, blk : 0, word: 4, pos : 2, len  : 1, start: 130, type      : bool, wr_dis  : 18, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[2]', bloc: 'B16[2]'}
  LOCK_KM_KEY                      : {show: y, blk : 0, word: 4, pos : 3, len  : 1, start: 131, type      : bool, wr_dis   : 1, rd_dis: null, alt                            : '', dict             : '', desc: TBD, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[3]', bloc: 'B16[3]'}
  DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE: {show: y, blk : 0, word: 4, pos : 4, len  : 1, start: 132, type      : bool, wr_dis  : 18, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[4]', bloc: 'B16[4]'}
  ENABLE_SECURITY_DOWNLOAD         : {show: y, blk : 0, word: 4, pos : 5, len  : 1, start: 133, type      : bool, wr_dis  : 18, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether security download is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[5]', bloc: 'B16[5]'}
  UART_PRINT_CONTROL               : {show: y, blk : 0, word: 4, pos : 6, len  : 2, start: 134, type  : 'uint:2', wr_dis  : 18, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents the type of UART printing. 00: force enable printing. 01: enable printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset at high level. 11: force disable printing', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[7:6]', bloc: 'B16[7:6]'}
  FORCE_SEND_RESUME                : {show: y, blk : 0, word: 4, pos : 8, len  : 1, start: 136, type      : bool, wr_dis  : 18, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[8]', bloc: 'B17[0]'}
  SECURE_VERSION                   : {show: y, blk : 0, word: 4, pos : 9, len : 16, start: 137, type : 'uint:16', wr_dis  : 18, rd_dis: null, alt                            : '', dict             : '', desc: Represents the version used by ESP-IDF anti-rollback feature, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[24:9]', bloc: 'B17[7:1],B18,B19[0]'}
  SECURE_BOOT_DISABLE_FAST_WAKE    : {show: y, blk : 0, word: 4, pos: 25, len  : 1, start: 153, type      : bool, wr_dis  : 18, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[25]', bloc: 'B19[1]'}
  HYS_EN_PAD                       : {show: y, blk : 0, word: 4, pos: 26, len  : 1, start: 154, type      : bool, wr_dis   : 2, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled. 0:disabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[26]', bloc: 'B19[2]'}
  DCDC_VSET                        : {show: y, blk : 0, word: 4, pos: 27, len  : 5, start: 155, type  : 'uint:5', wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: Set the dcdc voltage default, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[31:27]', bloc: 'B19[7:3]'}
  PXA0_TIEH_SEL_0                  : {show: y, blk : 0, word: 5, pos : 0, len  : 2, start: 160, type  : 'uint:2', wr_dis   : 2, rd_dis: null, alt                            : '', dict             : '', desc: TBD, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[1:0]', bloc: 'B20[1:0]'}
  PXA0_TIEH_SEL_1                  : {show: y, blk : 0, word: 5, pos : 2, len  : 2, start: 162, type  : 'uint:2', wr_dis   : 2, rd_dis: null, alt                            : '', dict             : '', desc: TBD, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[3:2]', bloc: 'B20[3:2]'}
  PXA0_TIEH_SEL_2                  : {show: y, blk : 0, word: 5, pos : 4, len  : 2, start: 164, type  : 'uint:2', wr_dis   : 2, rd_dis: null, alt                            : '', dict             : '', desc: TBD, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[5:4]', bloc: 'B20[5:4]'}
  PXA0_TIEH_SEL_3                  : {show: y, blk : 0, word: 5, pos : 6, len  : 2, start: 166, type  : 'uint:2', wr_dis   : 2, rd_dis: null, alt                            : '', dict             : '', desc: TBD, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[7:6]', bloc: 'B20[7:6]'}
  KM_DISABLE_DEPLOY_MODE           : {show: y, blk : 0, word: 5, pos : 8, len  : 4, start: 168, type  : 'uint:4', wr_dis   : 1, rd_dis: null, alt                            : '', dict             : '', desc: TBD, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[11:8]', bloc: 'B21[3:0]'}
  USB_DEVICE_DREFL                 : {show: n, blk : 0, word: 5, pos: 12, len  : 2, start: 172, type  : 'uint:2', wr_dis  : 30, rd_dis: null, alt                            : '', dict             : '', desc: Represents the usb device single-end input low threshold; 0.8 V to 1.04 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[13:12]', bloc: 'B21[5:4]'}
  USB_OTG11_DREFL                  : {show: n, blk : 0, word: 5, pos: 14, len  : 2, start: 174, type  : 'uint:2', wr_dis  : 30, rd_dis: null, alt                            : '', dict             : '', desc: Represents the usb otg11 single-end input low threshold; 0.8 V to 1.04 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[15:14]', bloc: 'B21[7:6]'}
  RESERVE_0_176                    : {show: n, blk : 0, word: 5, pos: 16, len  : 2, start: 176, type  : 'uint:2', wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[17:16]', bloc: 'B22[1:0]'}
  HP_PWR_SRC_SEL                   : {show: y, blk : 0, word: 5, pos: 18, len  : 1, start: 178, type      : bool, wr_dis   : 3, rd_dis: null, alt                            : '', dict             : '', desc: 'HP system power source select. 0:LDO. 1: DCDC', rloc: 'EFUSE_RD_REPEAT_DATA4_REG[18]', bloc: 'B22[2]'}
  DCDC_VSET_EN                     : {show: y, blk : 0, word: 5, pos: 19, len  : 1, start: 179, type      : bool, wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: Select dcdc vset use efuse_dcdc_vset, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[19]', bloc: 'B22[3]'}
  DIS_WDT                          : {show: y, blk : 0, word: 5, pos: 20, len  : 1, start: 180, type      : bool, wr_dis   : 2, rd_dis: null, alt                            : '', dict             : '', desc: Set this bit to disable watch dog, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[20]', bloc: 'B22[4]'}
  DIS_SWD                          : {show: y, blk : 0, word: 5, pos: 21, len  : 1, start: 181, type      : bool, wr_dis   : 2, rd_dis: null, alt                            : '', dict             : '', desc: Set this bit to disable super-watchdog, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[21]', bloc: 'B22[5]'}
  RESERVE_0_182                    : {show: n, blk : 0, word: 5, pos: 22, len : 10, start: 182, type : 'uint:10', wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[31:22]', bloc: 'B22[7:6],B23'}
  MAC                              : {show: y, blk : 1, word: 0, pos : 0, len : 48, start  : 0, type : 'bytes:6', wr_dis  : 20, rd_dis: null, alt                   : MAC_FACTORY, dict             : '', desc: MAC address, rloc: EFUSE_RD_MAC_SYS_0_REG, bloc: 'B0,B1,B2,B3,B4,B5'}
  RESERVED_1_16                    : {show: n, blk : 1, word: 1, pos: 16, len : 16, start : 48, type : 'uint:16', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: Stores the extended bits of MAC address, rloc: 'EFUSE_RD_MAC_SYS_1_REG[31:16]', bloc: 'B6,B7'}
  WAFER_VERSION_MINOR              : {show: y, blk : 1, word: 2, pos : 0, len  : 4, start : 64, type  : 'uint:4', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: Minor chip version, rloc: 'EFUSE_RD_MAC_SYS_2_REG[3:0]', bloc: 'B8[3:0]'}
  WAFER_VERSION_MAJOR_LO           : {show: y, blk : 1, word: 2, pos : 4, len  : 2, start : 68, type  : 'uint:2', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: Major chip version (lower 2 bits), rloc: 'EFUSE_RD_MAC_SYS_2_REG[5:4]', bloc: 'B8[5:4]'}
  DISABLE_WAFER_VERSION_MAJOR      : {show: y, blk : 1, word: 2, pos : 6, len  : 1, start : 70, type      : bool, wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: Disables check of wafer version major, rloc: 'EFUSE_RD_MAC_SYS_2_REG[6]', bloc: 'B8[6]'}
  DISABLE_BLK_VERSION_MAJOR        : {show: y, blk : 1, word: 2, pos : 7, len  : 1, start : 71, type      : bool, wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: Disables check of blk version major, rloc: 'EFUSE_RD_MAC_SYS_2_REG[7]', bloc: 'B8[7]'}
  BLK_VERSION_MINOR                : {show: y, blk : 1, word: 2, pos : 8, len  : 3, start : 72, type  : 'uint:3', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: BLK_VERSION_MINOR of BLOCK2, rloc: 'EFUSE_RD_MAC_SYS_2_REG[10:8]', bloc: 'B9[2:0]'}
  BLK_VERSION_MAJOR                : {show: y, blk : 1, word: 2, pos: 11, len  : 2, start : 75, type  : 'uint:2', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: BLK_VERSION_MAJOR of BLOCK2, rloc: 'EFUSE_RD_MAC_SYS_2_REG[12:11]', bloc: 'B9[4:3]'}
  PSRAM_CAP                        : {show: y, blk : 1, word: 2, pos: 13, len  : 3, start : 77, type  : 'uint:3', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: PSRAM capacity, rloc: 'EFUSE_RD_MAC_SYS_2_REG[15:13]', bloc: 'B9[7:5]'}
  TEMP                             : {show: y, blk : 1, word: 2, pos: 16, len  : 2, start : 80, type  : 'uint:2', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: Operating temperature of the ESP chip, rloc: 'EFUSE_RD_MAC_SYS_2_REG[17:16]', bloc: 'B10[1:0]'}
  PSRAM_VENDOR                     : {show: y, blk : 1, word: 2, pos: 18, len  : 2, start : 82, type  : 'uint:2', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: PSRAM vendor, rloc: 'EFUSE_RD_MAC_SYS_2_REG[19:18]', bloc: 'B10[3:2]'}
  PKG_VERSION                      : {show: y, blk : 1, word: 2, pos: 20, len  : 3, start : 84, type  : 'uint:3', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: Package version, rloc: 'EFUSE_RD_MAC_SYS_2_REG[22:20]', bloc: 'B10[6:4]'}
  WAFER_VERSION_MAJOR_HI           : {show: y, blk : 1, word: 2, pos: 23, len  : 1, start : 87, type      : bool, wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: Major chip version (MSB), rloc: 'EFUSE_RD_MAC_SYS_2_REG[23]', bloc: 'B10[7]'}
  LDO_VO1_DREF                     : {show: y, blk : 1, word: 2, pos: 24, len  : 4, start : 88, type  : 'uint:4', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: Output VO1 parameter, rloc: 'EFUSE_RD_MAC_SYS_2_REG[27:24]', bloc: 'B11[3:0]'}
  LDO_VO2_DREF                     : {show: y, blk : 1, word: 2, pos: 28, len  : 4, start : 92, type  : 'uint:4', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: Output VO2 parameter, rloc: 'EFUSE_RD_MAC_SYS_2_REG[31:28]', bloc: 'B11[7:4]'}
  LDO_VO1_MUL                      : {show: y, blk : 1, word: 3, pos : 0, len  : 3, start : 96, type  : 'uint:3', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: Output VO1 parameter, rloc: 'EFUSE_RD_MAC_SYS_3_REG[2:0]', bloc: 'B12[2:0]'}
  LDO_VO2_MUL                      : {show: y, blk : 1, word: 3, pos : 3, len  : 3, start : 99, type  : 'uint:3', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: Output VO2 parameter, rloc: 'EFUSE_RD_MAC_SYS_3_REG[5:3]', bloc: 'B12[5:3]'}
  LDO_VO3_K                        : {show: y, blk : 1, word: 3, pos : 6, len  : 8, start: 102, type  : 'uint:8', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: Output VO3 calibration parameter, rloc: 'EFUSE_RD_MAC_SYS_3_REG[13:6]', bloc: 'B12[7:6],B13[5:0]'}
  LDO_VO3_VOS                      : {show: y, blk : 1, word: 3, pos: 14, len  : 6, start: 110, type  : 'uint:6', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: Output VO3 calibration parameter, rloc: 'EFUSE_RD_MAC_SYS_3_REG[19:14]', bloc: 'B13[7:6],B14[3:0]'}
  LDO_VO3_C                        : {show: y, blk : 1, word: 3, pos: 20, len  : 6, start: 116, type  : 'uint:6', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: Output VO3 calibration parameter, rloc: 'EFUSE_RD_MAC_SYS_3_REG[25:20]', bloc: 'B14[7:4],B15[1:0]'}
  LDO_VO4_K                        : {show: y, blk : 1, word: 3, pos: 26, len  : 8, start: 122, type  : 'uint:8', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: Output VO4 calibration parameter, rloc: 'EFUSE_RD_MAC_SYS_3_REG[31:26]', bloc: 'B15[7:2],B16[1:0]'}
  LDO_VO4_VOS                      : {show: y, blk : 1, word: 4, pos : 2, len  : 6, start: 130, type  : 'uint:6', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: Output VO4 calibration parameter, rloc: 'EFUSE_RD_MAC_SYS_4_REG[7:2]', bloc: 'B16[7:2]'}
  LDO_VO4_C                        : {show: y, blk : 1, word: 4, pos : 8, len  : 6, start: 136, type  : 'uint:6', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: Output VO4 calibration parameter, rloc: 'EFUSE_RD_MAC_SYS_4_REG[13:8]', bloc: 'B17[5:0]'}
  RESERVED_1_142                   : {show: n, blk : 1, word: 4, pos: 14, len  : 2, start: 142, type  : 'uint:2', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: reserved, rloc: 'EFUSE_RD_MAC_SYS_4_REG[15:14]', bloc: 'B17[7:6]'}
  ACTIVE_HP_DBIAS                  : {show: y, blk : 1, word: 4, pos: 16, len  : 4, start: 144, type  : 'uint:4', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: Active HP DBIAS of fixed voltage, rloc: 'EFUSE_RD_MAC_SYS_4_REG[19:16]', bloc: 'B18[3:0]'}
  ACTIVE_LP_DBIAS                  : {show: y, blk : 1, word: 4, pos: 20, len  : 4, start: 148, type  : 'uint:4', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: Active LP DBIAS of fixed voltage, rloc: 'EFUSE_RD_MAC_SYS_4_REG[23:20]', bloc: 'B18[7:4]'}
  LSLP_HP_DBIAS                    : {show: y, blk : 1, word: 4, pos: 24, len  : 4, start: 152, type  : 'uint:4', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: LSLP HP DBIAS of fixed voltage, rloc: 'EFUSE_RD_MAC_SYS_4_REG[27:24]', bloc: 'B19[3:0]'}
  DSLP_DBG                         : {show: y, blk : 1, word: 4, pos: 28, len  : 4, start: 156, type  : 'uint:4', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: DSLP BDG of fixed voltage, rloc: 'EFUSE_RD_MAC_SYS_4_REG[31:28]', bloc: 'B19[7:4]'}
  DSLP_LP_DBIAS                    : {show: y, blk : 1, word: 5, pos : 0, len  : 5, start: 160, type  : 'uint:5', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: DSLP LP DBIAS of fixed voltage, rloc: 'EFUSE_RD_MAC_SYS_5_REG[4:0]', bloc: 'B20[4:0]'}
  LP_DCDC_DBIAS_VOL_GAP            : {show: y, blk : 1, word: 5, pos : 5, len  : 5, start: 165, type  : 'uint:5', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: DBIAS gap between LP and DCDC, rloc: 'EFUSE_RD_MAC_SYS_5_REG[9:5]', bloc: 'B20[7:5],B21[1:0]'}
  RESERVED_1_170                   : {show: n, blk : 1, word: 5, pos: 10, len : 22, start: 170, type : 'uint:22', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: reserved, rloc: 'EFUSE_RD_MAC_SYS_5_REG[31:10]', bloc: 'B21[7:2],B22,B23'}
  OPTIONAL_UNIQUE_ID               : {show: y, blk : 2, word: 0, pos : 0, len: 128, start  : 0, type: 'bytes:16', wr_dis  : 21, rd_dis: null, alt                            : '', dict             : '', desc: Optional unique 128-bit ID, rloc: EFUSE_RD_SYS_PART1_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15'}
  ADC1_AVE_INITCODE_ATTEN0         : {show: y, blk : 2, word: 4, pos : 0, len : 10, start: 128, type : 'uint:10', wr_dis  : 21, rd_dis: null, alt                            : '', dict             : '', desc: Average initcode of ADC1 atten0, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[9:0]', bloc: 'B16,B17[1:0]'}
  ADC1_AVE_INITCODE_ATTEN1         : {show: y, blk : 2, word: 4, pos: 10, len : 10, start: 138, type : 'uint:10', wr_dis  : 21, rd_dis: null, alt                            : '', dict             : '', desc: Average initcode of ADC1 atten1, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[19:10]', bloc: 'B17[7:2],B18[3:0]'}
  ADC1_AVE_INITCODE_ATTEN2         : {show: y, blk : 2, word: 4, pos: 20, len : 10, start: 148, type : 'uint:10', wr_dis  : 21, rd_dis: null, alt                            : '', dict             : '', desc: Average initcode of ADC1 atten2, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[29:20]', bloc: 'B18[7:4],B19[5:0]'}
  ADC1_AVE_INITCODE_ATTEN3         : {show: y, blk : 2, word: 4, pos: 30, len : 10, start: 158, type : 'uint:10', wr_dis  : 21, rd_dis: null, alt                            : '', dict             : '', desc: Average initcode of ADC1 atten3, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[31:30]', bloc: 'B19[7:6],B20'}
  ADC2_AVE_INITCODE_ATTEN0         : {show: y, blk : 2, word: 5, pos : 8, len : 10, start: 168, type : 'uint:10', wr_dis  : 21, rd_dis: null, alt                            : '', dict             : '', desc: Average initcode of ADC2 atten0, rloc: 'EFUSE_RD_SYS_PART1_DATA5_REG[17:8]', bloc: 'B21,B22[1:0]'}
  ADC2_AVE_INITCODE_ATTEN1         : {show: y, blk : 2, word: 5, pos: 18, len : 10, start: 178, type : 'uint:10', wr_dis  : 21, rd_dis: null, alt                            : '', dict             : '', desc: Average initcode of ADC2 atten1, rloc: 'EFUSE_RD_SYS_PART1_DATA5_REG[27:18]', bloc: 'B22[7:2],B23[3:0]'}
  ADC2_AVE_INITCODE_ATTEN2         : {show: y, blk : 2, word: 5, pos: 28, len : 10, start: 188, type : 'uint:10', wr_dis  : 21, rd_dis: null, alt                            : '', dict             : '', desc: Average initcode of ADC2 atten2, rloc: 'EFUSE_RD_SYS_PART1_DATA5_REG[31:28]', bloc: 'B23[7:4],B24[5:0]'}
  ADC2_AVE_INITCODE_ATTEN3         : {show: y, blk : 2, word: 6, pos : 6, len : 10, start: 198, type : 'uint:10', wr_dis  : 21, rd_dis: null, alt                            : '', dict             : '', desc: Average initcode of ADC2 atten3, rloc: 'EFUSE_RD_SYS_PART1_DATA6_REG[15:6]', bloc: 'B24[7:6],B25'}
  ADC1_HI_DOUT_ATTEN0              : {show: y, blk : 2, word: 6, pos: 16, len : 10, start: 208, type : 'uint:10', wr_dis  : 21, rd_dis: null, alt                            : '', dict             : '', desc: HI_DOUT of ADC1 atten0, rloc: 'EFUSE_RD_SYS_PART1_DATA6_REG[25:16]', bloc: 'B26,B27[1:0]'}
  ADC1_HI_DOUT_ATTEN1              : {show: y, blk : 2, word: 6, pos: 26, len : 10, start: 218, type : 'uint:10', wr_dis  : 21, rd_dis: null, alt                            : '', dict             : '', desc: HI_DOUT of ADC1 atten1, rloc: 'EFUSE_RD_SYS_PART1_DATA6_REG[31:26]', bloc: 'B27[7:2],B28[3:0]'}
  ADC1_HI_DOUT_ATTEN2              : {show: y, blk : 2, word: 7, pos : 4, len : 10, start: 228, type : 'uint:10', wr_dis  : 21, rd_dis: null, alt                            : '', dict             : '', desc: HI_DOUT of ADC1 atten2, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[13:4]', bloc: 'B28[7:4],B29[5:0]'}
  ADC1_HI_DOUT_ATTEN3              : {show: y, blk : 2, word: 7, pos: 14, len : 10, start: 238, type : 'uint:10', wr_dis  : 21, rd_dis: null, alt                            : '', dict             : '', desc: HI_DOUT of ADC1 atten3, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[23:14]', bloc: 'B29[7:6],B30'}
  RESERVED_2_248                   : {show: n, blk : 2, word: 7, pos: 24, len  : 8, start: 248, type  : 'uint:8', wr_dis  : 21, rd_dis: null, alt                            : '', dict             : '', desc: reserved, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[31:24]', bloc: B31}
  BLOCK_USR_DATA                   : {show: y, blk : 3, word: 0, pos : 0, len: 192, start  : 0, type: 'bytes:24', wr_dis  : 22, rd_dis: null, alt                     : USER_DATA, dict             : '', desc: User data, rloc: EFUSE_RD_USR_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23'}
  RESERVED_3_192                   : {show: n, blk : 3, word: 6, pos : 0, len  : 8, start: 192, type  : 'uint:8', wr_dis  : 22, rd_dis: null, alt                            : '', dict             : '', desc: reserved, rloc: 'EFUSE_RD_USR_DATA6_REG[7:0]', bloc: B24}
  CUSTOM_MAC                       : {show: y, blk : 3, word: 6, pos : 8, len : 48, start: 200, type : 'bytes:6', wr_dis  : 22, rd_dis: null, alt: MAC_CUSTOM USER_DATA_MAC_CUSTOM, dict             : '', desc: Custom MAC, rloc: 'EFUSE_RD_USR_DATA6_REG[31:8]', bloc: 'B25,B26,B27,B28,B29,B30'}
  RESERVED_3_248                   : {show: n, blk : 3, word: 7, pos: 24, len  : 8, start: 248, type  : 'uint:8', wr_dis  : 22, rd_dis: null, alt                            : '', dict             : '', desc: reserved, rloc: 'EFUSE_RD_USR_DATA7_REG[31:24]', bloc: B31}
  BLOCK_KEY0                       : {show: y, blk : 4, word: 0, pos : 0, len: 256, start  : 0, type: 'bytes:32', wr_dis  : 23, rd_dis   : 0, alt                          : KEY0, dict             : '', desc: Key0 or user data, rloc: EFUSE_RD_KEY0_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'}
  BLOCK_KEY1                       : {show: y, blk : 5, word: 0, pos : 0, len: 256, start  : 0, type: 'bytes:32', wr_dis  : 24, rd_dis   : 1, alt                          : KEY1, dict             : '', desc: Key1 or user data, rloc: EFUSE_RD_KEY1_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'}
  BLOCK_KEY2                       : {show: y, blk : 6, word: 0, pos : 0, len: 256, start  : 0, type: 'bytes:32', wr_dis  : 25, rd_dis   : 2, alt                          : KEY2, dict             : '', desc: Key2 or user data, rloc: EFUSE_RD_KEY2_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'}
  BLOCK_KEY3                       : {show: y, blk : 7, word: 0, pos : 0, len: 256, start  : 0, type: 'bytes:32', wr_dis  : 26, rd_dis   : 3, alt                          : KEY3, dict             : '', desc: Key3 or user data, rloc: EFUSE_RD_KEY3_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'}
  BLOCK_KEY4                       : {show: y, blk : 8, word: 0, pos : 0, len: 256, start  : 0, type: 'bytes:32', wr_dis  : 27, rd_dis   : 4, alt                          : KEY4, dict             : '', desc: Key4 or user data, rloc: EFUSE_RD_KEY4_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'}
  BLOCK_KEY5                       : {show: y, blk : 9, word: 0, pos : 0, len: 256, start  : 0, type: 'bytes:32', wr_dis  : 28, rd_dis   : 5, alt                          : KEY5, dict             : '', desc: Key5 or user data, rloc: EFUSE_RD_KEY5_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'}
  ADC2_HI_DOUT_ATTEN0              : {show: y, blk: 10, word: 0, pos : 0, len : 10, start  : 0, type : 'uint:10', wr_dis  : 29, rd_dis   : 6, alt                            : '', dict             : '', desc: HI_DOUT of ADC2 atten0, rloc: 'EFUSE_RD_SYS_PART2_DATA0_REG[9:0]', bloc: 'B0,B1[1:0]'}
  ADC2_HI_DOUT_ATTEN1              : {show: y, blk: 10, word: 0, pos: 10, len : 10, start : 10, type : 'uint:10', wr_dis  : 29, rd_dis   : 6, alt                            : '', dict             : '', desc: HI_DOUT of ADC2 atten1, rloc: 'EFUSE_RD_SYS_PART2_DATA0_REG[19:10]', bloc: 'B1[7:2],B2[3:0]'}
  ADC2_HI_DOUT_ATTEN2              : {show: y, blk: 10, word: 0, pos: 20, len : 10, start : 20, type : 'uint:10', wr_dis  : 29, rd_dis   : 6, alt                            : '', dict             : '', desc: HI_DOUT of ADC2 atten2, rloc: 'EFUSE_RD_SYS_PART2_DATA0_REG[29:20]', bloc: 'B2[7:4],B3[5:0]'}
  ADC2_HI_DOUT_ATTEN3              : {show: y, blk: 10, word: 0, pos: 30, len : 10, start : 30, type : 'uint:10', wr_dis  : 29, rd_dis   : 6, alt                            : '', dict             : '', desc: HI_DOUT of ADC2 atten3, rloc: 'EFUSE_RD_SYS_PART2_DATA0_REG[31:30]', bloc: 'B3[7:6],B4'}
  ADC1_CH0_ATTEN0_INITCODE_DIFF    : {show: y, blk: 10, word: 1, pos : 8, len  : 4, start : 40, type  : 'uint:4', wr_dis  : 29, rd_dis   : 6, alt                            : '', dict             : '', desc: Gap between ADC1_ch0 and average initcode, rloc: 'EFUSE_RD_SYS_PART2_DATA1_REG[11:8]', bloc: 'B5[3:0]'}
  ADC1_CH1_ATTEN0_INITCODE_DIFF    : {show: y, blk: 10, word: 1, pos: 12, len  : 4, start : 44, type  : 'uint:4', wr_dis  : 29, rd_dis   : 6, alt                            : '', dict             : '', desc: Gap between ADC1_ch1 and average initcode, rloc: 'EFUSE_RD_SYS_PART2_DATA1_REG[15:12]', bloc: 'B5[7:4]'}
  ADC1_CH2_ATTEN0_INITCODE_DIFF    : {show: y, blk: 10, word: 1, pos: 16, len  : 4, start : 48, type  : 'uint:4', wr_dis  : 29, rd_dis   : 6, alt                            : '', dict             : '', desc: Gap between ADC1_ch2 and average initcode, rloc: 'EFUSE_RD_SYS_PART2_DATA1_REG[19:16]', bloc: 'B6[3:0]'}
  ADC1_CH3_ATTEN0_INITCODE_DIFF    : {show: y, blk: 10, word: 1, pos: 20, len  : 4, start : 52, type  : 'uint:4', wr_dis  : 29, rd_dis   : 6, alt                            : '', dict             : '', desc: Gap between ADC1_ch3 and average initcode, rloc: 'EFUSE_RD_SYS_PART2_DATA1_REG[23:20]', bloc: 'B6[7:4]'}
  ADC1_CH4_ATTEN0_INITCODE_DIFF    : {show: y, blk: 10, word: 1, pos: 24, len  : 4, start : 56, type  : 'uint:4', wr_dis  : 29, rd_dis   : 6, alt                            : '', dict             : '', desc: Gap between ADC1_ch4 and average initcode, rloc: 'EFUSE_RD_SYS_PART2_DATA1_REG[27:24]', bloc: 'B7[3:0]'}
  ADC1_CH5_ATTEN0_INITCODE_DIFF    : {show: y, blk: 10, word: 1, pos: 28, len  : 4, start : 60, type  : 'uint:4', wr_dis  : 29, rd_dis   : 6, alt                            : '', dict             : '', desc: Gap between ADC1_ch5 and average initcode, rloc: 'EFUSE_RD_SYS_PART2_DATA1_REG[31:28]', bloc: 'B7[7:4]'}
  ADC1_CH6_ATTEN0_INITCODE_DIFF    : {show: y, blk: 10, word: 2, pos : 0, len  : 4, start : 64, type  : 'uint:4', wr_dis  : 29, rd_dis   : 6, alt                            : '', dict             : '', desc: Gap between ADC1_ch6 and average initcode, rloc: 'EFUSE_RD_SYS_PART2_DATA2_REG[3:0]', bloc: 'B8[3:0]'}
  ADC1_CH7_ATTEN0_INITCODE_DIFF    : {show: y, blk: 10, word: 2, pos : 4, len  : 4, start : 68, type  : 'uint:4', wr_dis  : 29, rd_dis   : 6, alt                            : '', dict             : '', desc: Gap between ADC1_ch7 and average initcode, rloc: 'EFUSE_RD_SYS_PART2_DATA2_REG[7:4]', bloc: 'B8[7:4]'}
  ADC2_CH0_ATTEN0_INITCODE_DIFF    : {show: y, blk: 10, word: 2, pos : 8, len  : 4, start : 72, type  : 'uint:4', wr_dis  : 29, rd_dis   : 6, alt                            : '', dict             : '', desc: Gap between ADC2_ch0 and average initcode, rloc: 'EFUSE_RD_SYS_PART2_DATA2_REG[11:8]', bloc: 'B9[3:0]'}
  ADC2_CH1_ATTEN0_INITCODE_DIFF    : {show: y, blk: 10, word: 2, pos: 12, len  : 4, start : 76, type  : 'uint:4', wr_dis  : 29, rd_dis   : 6, alt                            : '', dict             : '', desc: Gap between ADC2_ch1 and average initcode, rloc: 'EFUSE_RD_SYS_PART2_DATA2_REG[15:12]', bloc: 'B9[7:4]'}
  ADC2_CH2_ATTEN0_INITCODE_DIFF    : {show: y, blk: 10, word: 2, pos: 16, len  : 4, start : 80, type  : 'uint:4', wr_dis  : 29, rd_dis   : 6, alt                            : '', dict             : '', desc: Gap between ADC2_ch2 and average initcode, rloc: 'EFUSE_RD_SYS_PART2_DATA2_REG[19:16]', bloc: 'B10[3:0]'}
  ADC2_CH3_ATTEN0_INITCODE_DIFF    : {show: y, blk: 10, word: 2, pos: 20, len  : 4, start : 84, type  : 'uint:4', wr_dis  : 29, rd_dis   : 6, alt                            : '', dict             : '', desc: Gap between ADC2_ch3 and average initcode, rloc: 'EFUSE_RD_SYS_PART2_DATA2_REG[23:20]', bloc: 'B10[7:4]'}
  ADC2_CH4_ATTEN0_INITCODE_DIFF    : {show: y, blk: 10, word: 2, pos: 24, len  : 4, start : 88, type  : 'uint:4', wr_dis  : 29, rd_dis   : 6, alt                            : '', dict             : '', desc: Gap between ADC2_ch4 and average initcode, rloc: 'EFUSE_RD_SYS_PART2_DATA2_REG[27:24]', bloc: 'B11[3:0]'}
  ADC2_CH5_ATTEN0_INITCODE_DIFF    : {show: y, blk: 10, word: 2, pos: 28, len  : 4, start : 92, type  : 'uint:4', wr_dis  : 29, rd_dis   : 6, alt                            : '', dict             : '', desc: Gap between ADC2_ch5 and average initcode, rloc: 'EFUSE_RD_SYS_PART2_DATA2_REG[31:28]', bloc: 'B11[7:4]'}
  TEMPERATURE_SENSOR               : {show: y, blk: 10, word: 3, pos : 0, len  : 9, start : 96, type  : 'uint:9', wr_dis  : 29, rd_dis   : 6, alt                            : '', dict             : '', desc: Temperature calibration data, rloc: 'EFUSE_RD_SYS_PART2_DATA3_REG[8:0]', bloc: 'B12,B13[0]'}
  RESERVED_10_105                  : {show: n, blk: 10, word: 3, pos : 9, len : 23, start: 105, type : 'uint:23', wr_dis  : 29, rd_dis   : 6, alt                            : '', dict             : '', desc: reserved, rloc: 'EFUSE_RD_SYS_PART2_DATA3_REG[31:9]', bloc: 'B13[7:1],B14,B15'}
  SYS_DATA_PART2_4                 : {show: n, blk: 10, word: 4, pos : 0, len : 32, start: 128, type : 'uint:32', wr_dis  : 29, rd_dis   : 6, alt                            : '', dict             : '', desc: Stores the $nth 32 bits of the 2nd part of system data, rloc: EFUSE_RD_SYS_PART2_DATA4_REG, bloc: 'B16,B17,B18,B19'}
  SYS_DATA_PART2_5                 : {show: n, blk: 10, word: 5, pos : 0, len : 32, start: 160, type : 'uint:32', wr_dis  : 29, rd_dis   : 6, alt                            : '', dict             : '', desc: Stores the $nth 32 bits of the 2nd part of system data, rloc: EFUSE_RD_SYS_PART2_DATA5_REG, bloc: 'B20,B21,B22,B23'}
  SYS_DATA_PART2_6                 : {show: n, blk: 10, word: 6, pos : 0, len : 32, start: 192, type : 'uint:32', wr_dis  : 29, rd_dis   : 6, alt                            : '', dict             : '', desc: Stores the $nth 32 bits of the 2nd part of system data, rloc: EFUSE_RD_SYS_PART2_DATA6_REG, bloc: 'B24,B25,B26,B27'}
  SYS_DATA_PART2_7                 : {show: n, blk: 10, word: 7, pos : 0, len : 32, start: 224, type : 'uint:32', wr_dis  : 29, rd_dis   : 6, alt                            : '', dict             : '', desc: Stores the $nth 32 bits of the 2nd part of system data, rloc: EFUSE_RD_SYS_PART2_DATA7_REG, bloc: 'B28,B29,B30,B31'}
